Modern micro-chips employ clock gating cells for power saving. A CPU in the micro-chip is operated by a clock signal (generated by a PLL, for example), called a ‘root’ clock, which is used to operate blocks within the micro-chip. When a block is not required to be operated, its clock input can be gated off by connecting the root clock to a clock gating cell which generates a clock output depending on the logic level of an enable signal. Please refer to FIG. 1A, which is a diagram of a conventional clock gating cell 100. As shown in the diagram, the clock gating cell 100 comprises an active-low latch circuit 120 that receives a clock input signal and an enable input signal. The output of the latch circuit 120 is the first input of an AND logic gate 130 which is coupled to the latch circuit 120, and the clock signal is the second input of the AND gate 130. When the enable signal EN is logic 0, the clock will be gated off. When the enable signal EN is logic 1, the AND gate 130 will generate an output clock ENCK.
By only generating an output clock to certain blocks when they are required to be operated, dynamic power within the system can be saved. Even when the enable signal EN is at logic 0, however, the clock gating cell 100 itself will consume power as the clock input signal is always active. The amount of power consumed may be significant.
Please refer to FIG. 2, which is a diagram showing the internal structure of the clock gating cell 100 illustrated in FIG. 1A. Please note that, in the following descriptions, where a number of transistors are coupled together, the transistor which is coupled to the power supply will be designated as the first transistor, the next transistor will be designated as the second transistor, and so on. As shown in the diagram, the enable signal EN is input to a first transistor and a fourth transistor of a first plurality of transistors. The first transistor is coupled to a power supply and the fourth transistor is coupled to ground. The clock signal CK is input to an inverter for generating an inverted clock signal CKZ, which is then input to another inverter for generating a clock signal CK1, which will be out of phase with the original clock signal CK. The first plurality of transistors also comprises a second transistor and a third transistor, which are coupled in series between the first transistor and the fourth transistor. The gate of the second transistor receives the input CK1 and the gate of the third transistor receives the input CKZ. The drain of the second transistor and the source of the third transistors are coupled to an inverter and a second plurality of transistors, which comprises four transistors coupled in series. More specifically, the output of the first plurality of transistors is coupled to the drain of the second transistor and the source of the third transistor of the second plurality of transistors. In the second plurality of transistors, the gate of the second transistor receives the input CK1 and the gate of the third transistor receives the input CKZ. The gates of the first and fourth transistor are coupled to the output of the inverter. The AND gate receives the output of the inverter as a first input and the clock signal CK as a second input. An inverse enable clock signal ENCKZ is generated and input to an inverter, which generates the enabled clock signal ENCK.
The transistors which are circled in the diagram all receive a clock signal as an input. Even when the enable signal is at logic 0, these transistors will still toggle with the clock signal CK. In the circuit 100, out of a total of 20 transistors, 10 transistors (i.e. 50%) will toggle with the clock signal CK.
Furthermore, a typical micro-chip comprises many clock gating cells connected to the root clock. Please refer to FIG. 1B, which illustrates the connection of clock gating cells 100 to the root clock. As shown in the diagram, the CPU 170 will generate the root clock, which is input to many clock gating cells 100. As long as the CPU 170 is kept ON, all clock gating cells coupled to the root clock will have 50% of their transistors toggling even when they are not enabled. In a standard micro-chip, there may be as many as 5000 clock gating cells coupled to the root clock.
There is therefore a significant problem of power consumption in a conventional clock gating cell.